PowerElecHub

Control Block Diagrams: FOC, PFC and LLC

Most power converters are controlled by loops inside loops. A fast inner loop regulates a quantity that changes quickly, usually a current, and a slower outer loop regulates what the application cares about, such as speed or output voltage, by moving the inner loop's reference. The diagrams below show three common structures. Each block can be clicked for its role and rate, and the step-through follows the signal around the loop in order, with example values on every edge.

Example operating point: PMSM with four pole pairs at 1450 rpm, speed reference 1500 rpm, V_dc = 24 V, R = 0.2 Ω, L_d = L_q = 1 mH, ψ = 0.01 Wb, rotor angle θ = 37°. Controller outputs are the steady-state values for the measured currents.

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Field-oriented control (PMSM)
i_q*v_q*i_d*v_d*v_αβ*abci_a, i_bi_αβi_di_qθθω*ΣPIspeedΣPI i_qi_d*ΣPI i_dInverseParkSVPWMInverterPMSMADCClarkeParkPosition /speedω̂ = 1450 rpm

Σ

ω* = 1500 rpmω̂ = 1450 rpmΔω = 50 rpm

The speed reference of 1500 rpm is compared with the estimated 1450 rpm. The 50 rpm error is what the speed controller has to remove.

Every Σ forms reference minus feedback. Transforms follow the Clarke/Park visual: amplitude-invariant scaling, d axis on phase a at θ = 0.

Σ summing junction

Speed error ω* − ω̂. It is updated at the speed-loop rate, often a fraction of the current-loop rate.

Click, tap or tab to any block to see what it does, how fast it runs relative to the others, and which page on this site covers it.

Bandwidth separation (illustrative)

1 Hz10 Hz100 Hz1 kHz10 kHz100 kHz1 MHzspeed loop 100 Hzcurrent loop 1.5 kHzPWM 20 kHz

Illustrative values for a typical design, not requirements. What matters is the separation: each inner loop several times faster than the loop around it, and every loop well below the sampling or switching rate.

Why cascaded loops work

If the inner loop is several times faster than the outer one, the outer loop sees it as an almost ideal actuator: ask for a current and the current is there. Each loop can then be tuned on its own. The usual rule of thumb is a factor of five to ten between the crossover frequencies, and every loop well below the rate at which it is sampled or switched.

The structure also gives natural places for limits. Clamping the inner reference limits the current, which protects the switches and the machine. When a clamp is active the outer integrator must stop accumulating, which is what anti-windup does.

Field-oriented control

In field-oriented control of a permanent-magnet synchronous machine, the speed controller produces a torque-producing current reference i_q*, and the flux strategy sets i_d*. Two current controllers work in the rotating dq frame, where the currents are constant in steady state. Their voltage commands pass through the inverse Park transform and space vector modulation to the inverter.

The feedback path runs the other way: the ADC samples the phase currents at a fixed point of the PWM period, the Clarke and Park transforms bring them into the dq frame, and an encoder or observer supplies the rotor angle for both transforms and the speed estimate for the outer loop. The Clarke/Park, SVPWM and PWM–ADC timing visuals on this site show those blocks in motion.

The dual-loop boost PFC

An average-current-mode PFC must draw a sinusoidal current while holding a constant DC bus. The inner current loop follows a reference shaped like the rectified line voltage and needs a crossover of several kilohertz. The outer voltage loop sets only the amplitude of that reference. It must be slow, typically 10 to 20 Hz, because the bus voltage carries a ripple at twice the line frequency; a faster loop would copy that ripple into the current reference and distort the input current.

Dividing the reference by the square of the RMS line voltage keeps the voltage-loop gain the same from low line to high line. The PFC loop calculator on this site computes both loops along the lines of TI application note U-134, and the boost PFC calculator sizes the power stage.

The LLC voltage loop

An LLC converter is controlled by frequency rather than duty cycle. The compensator output becomes a frequency command, and the resonant tank turns frequency into gain. Above resonance a higher frequency means less output, so the loop must raise the frequency when the output is too high; the sign is the opposite of a buck converter's duty loop.

The plant changes considerably with load and input voltage, and the feedback usually crosses an isolation barrier through an optocoupler, which adds a pole and a gain spread of its own. Check the loop at the corners of the operating range rather than at one point. The LLC design calculator shows the tank gain curves, and the LLC loop calculator plots the compensated loop.

Reading the diagrams

The bandwidth strip under each diagram gives illustrative values for a typical design: they show the separation between loops, not targets for your converter. Turn on the loop view to see which blocks belong to the inner and outer loop, and click a block for links to the calculator or visual that covers it in detail.

The animation follows the equations stated on this page. Conventions differ between textbooks and software libraries; check the one your code uses before comparing numbers.