Designing a Type II Compensator with the k-Factor Method

The usual circuit is an inverting error amplifier. The output voltage reaches the inverting input through the upper divider resistor R1, and the feedback network from the amplifier output back to that input is R2 in series with C1, with C2 in parallel across both. The lower divider resistor sets the DC operating point but, because the inverting input is a virtual ground, it does not appear in the small-signal transfer function.

Transfer function

Gc(s) = (1 + s·R2·C1) / [ s·R1·(C1 + C2) · (1 + s·R2·C1·C2 / (C1 + C2)) ]

Zero

f_z = 1 / (2π · R2 · C1)

Pole

f_p = (C1 + C2) / (2π · R2 · C1 · C2) ≈ 1 / (2π · R2 · C2) when C1 ≫ C2

At low frequency the integrator gives −90° of phase. Between the zero and the pole the phase rises again, and it peaks at the geometric mean of the two frequencies. That peak is the phase boost. The more the pole and zero are spread apart, the larger the boost, but it can never reach 90°, and a wide spread also raises the high-frequency gain, which lets more switching ripple into the loop.

With peak current-mode control, the inductor behaves roughly like a current source set by the control voltage, so the LC double pole of a voltage-mode buck splits into a single low-frequency pole formed by the output capacitor and the load. A first-order model that is good well below the switching frequency is:

Control-to-output gain

Gvc(s) = (R / Ri) · (1 + s·ESR·C) / (1 + s·R·C)

Load pole

f_pl = 1 / (2π · R · C)

ESR zero

f_esr = 1 / (2π · ESR · C)

Here R is the load resistance, C the output capacitance and Ri the current-sense gain in volts per ampere, referred to the error-amplifier output. Many controllers put an internal gain or a divider between the COMP pin and the current comparator, so take Ri from the datasheet's COMP-to-current transconductance rather than from the sense resistor alone. Between the load pole and the ESR zero the plant phase sits close to −90°, which is exactly the situation a Type II compensator is designed for.

This model leaves out the current-loop sampling effect, slope compensation details and the error amplifier's own bandwidth. The interactive plot below can add the sampling effect so you can see how much phase it costs.

The method places the zero a factor k below the crossover and the pole a factor k above it, so the maximum phase boost lands exactly at the crossover. For the Type II transfer function above, the following relations are exact, not approximations, once the plant gain and phase at fc are known.

1. 1Choose the crossover frequency fc. For peak current mode a common starting point is fs/10 or lower, and well above the load pole.
2. 2Evaluate the plant at fc: its gain |Gvc(fc)| and phase P (a negative number of degrees).
3. 3Choose the phase margin PM, typically 45° to 60°, and compute the required boost: Boost = PM − P − 90°.
4. 4Compute k = tan(Boost / 2 + 45°). The zero goes at fc/k and the pole at fc·k.
5. 5The compensator must have a gain of G = 1 / |Gvc(fc)| at fc so that the loop gain is exactly 1 there.
6. 6Pick R1 (it also sets the divider current) and compute C2 = 1 / (2π·fc·G·R1·k), C1 = C2·(k² − 1) and R2 = k / (2π·fc·C1).
7. 7Round to standard values and recheck the crossover and phase margin with the rounded parts.

Required boost

Boost = PM − P − 90°

k factor

k = tan(Boost / 2 + 45°)

Components

C2 = 1 / (2π·fc·G·R1·k), C1 = C2·(k² − 1), R2 = k / (2π·fc·C1)

Change the power stage or the targets and the plot recomputes the components and the loop. The check line reads the crossover and phase margin from the computed loop itself, so you can see that the formulas hit the target for the simple plant, and how far the result moves once the sampling pole at half the switching frequency is included.

1. 1Power stage: R = 12 V / 5 A = 2.4 Ω, C = 100 µF of ceramic capacitors with 3 mΩ total ESR, Ri = 0.25 V/A, fs = 500 kHz. The load pole is at 663 Hz and the ESR zero at about 530 kHz.
2. 2Targets: fc = 40 kHz (fs/12.5) and PM = 60°. With R1 = 10 kΩ.
3. 3Plant at 40 kHz: |Gvc| = 0.160 (−15.9 dB) and P = −84.7°.
4. 4Boost = 60° + 84.7° − 90° = 54.7°, so k = tan(72.4°) ≈ 3.15. The zero lands at 12.7 kHz and the pole at 126 kHz.
5. 5G = 1 / 0.160 ≈ 6.27. C2 = 1 / (2π · 40 kHz · 6.27 · 10 kΩ · 3.15) ≈ 20.2 pF, C1 = 20.2 pF · (3.15² − 1) ≈ 180 pF, R2 = 3.15 / (2π · 40 kHz · 180 pF) ≈ 69.7 kΩ.
6. 6With standard parts R2 = 68 kΩ, C1 = 180 pF and C2 = 22 pF, the computed loop crosses at about 38.8 kHz with a 58.6° phase margin.
7. 7Adding the sampling double pole at 250 kHz with Q = 2/π drops the phase margin to roughly 45° at the same crossover. That is still acceptable, but it shows that a 60° design on paper is not 60° on the bench.

The figures above were computed numerically from the models in this guide. They have not been compared with a measured converter, and the Q = 2/π sampling model is an assumption explained in the next section.

• Current-loop sampling. Ridley's current-mode model adds a double pole at half the switching frequency. Its quality factor is Q = 1 / (π · (m_c · D' − 0.5)), where m_c is the slope-compensation factor and D' = 1 − D. Q = 2/π corresponds to m_c · D' = 1. Less slope compensation gives a higher Q and more phase loss near fc, so check the value for your own controller.
• Error-amplifier bandwidth. An op-amp or transconductance amplifier with limited gain-bandwidth adds its own pole. Keep its gain-bandwidth comfortably above the compensator's gain at fp, or include it in the model.
• Transconductance amplifiers. Many integrated controllers use a gm amplifier with the RC network from COMP to ground instead of in the feedback path. The pole and zero follow the same idea, but the gain formulas are different, and the divider ratio does enter the loop gain.
• Optocoupler feedback. In an isolated supply using a TL431 and an optocoupler, the optocoupler's current transfer ratio and its own pole change the loop, and the classic circuit adds a second path through the LED resistor. The k-factor idea still applies, but not the component formulas above.
• Voltage-mode control. A voltage-mode buck has an LC double pole with up to −180° of phase, which a Type II cannot recover. That case needs a Type III compensator with two zeros and two poles.
• Tolerance and operating point. The load pole moves with load current and the capacitance of ceramic capacitors drops with DC bias, so recheck the margin at minimum and maximum load and at the derated capacitance.

• Using the sense resistor value as Ri and forgetting an internal current-sense amplifier gain or a COMP divider, which puts the crossover a factor of several away from the target.
• Placing the crossover too close to fs/2, where the simplified plant no longer describes the converter.
• Using the nominal capacitance of ceramic capacitors instead of the value at the actual DC bias.
• Reading the phase margin off the design targets instead of recomputing it with rounded standard values and, ideally, measuring the loop with a network analyzer by injecting a signal across a small resistor in the feedback path.
• Setting a very large phase boost to chase a high phase margin. The high-frequency gain rises with k, so switching ripple at the COMP pin can disturb the PWM comparator.

• H. D. Venable, "The K Factor: A New Mathematical Tool for Stability Analysis and Synthesis," Proceedings of Powercon 10, 1983.
• R. B. Ridley, "A New, Continuous-Time Model for Current-Mode Control," IEEE Transactions on Power Electronics, vol. 6, no. 2, 1991.