Sizing the DC-Link Capacitor of a Three-Phase Inverter by RMS Current
By the Power Electronics Hub editor · Published 2026-11-01
A 400 V inverter delivering 50 A rms per phase at M = 0.8 and cos φ = 0.9 puts about 30 A rms through its DC-link capacitor, almost all of it near the switching frequency and its multiples. That number, more than the capacitance, usually decides how big the bank is. It also doesn’t peak at full voltage: the worst case is near M = 0.6.
What the capacitor actually sees
The phase currents are smooth sinusoids at the fundamental, but the DC link does not see them directly. In each switching period the bridge connects phase currents to the DC rail in pieces, so the current drawn from the link is a train of pulses, i_dc = s_a·i_a + s_b·i_b + s_c·i_c. Its average is the real power divided by U_dc, and that is what the DC source provides. The capacitor supplies the rest.
With balanced sinusoidal currents there is no fundamental-frequency or double-frequency term in i_dc, unlike a single-phase inverter, where the 2f ripple dominates. So the capacitor current is high-frequency. A fundamental frequency of 50 Hz or 400 Hz hardly changes it, and neither does the switching frequency: in the simulation below, 5 kHz and 20 kHz give the same RMS to five digits.
The formula
- Capacitor RMS current (Kolar & Round)
- I_C,rms = I_N,rms · √( 2M · [ √3/(4π) + cos²φ · (√3/π − 9M/16) ] )
- Same thing with the peak phase current Î
- I_C,rms = Î · √( M · [ √3/(4π) + cos²φ · (√3/π − 9M/16) ] )
- Modulation index
- M = Û_phase / (U_dc / 2)
- Average DC current
- I_dc = (3/4) · M · Î · cos φ
The current in front of the root is the RMS phase current. Using the peak there reads 41 % too high, as the simulation below shows.
As a check, an ideal three-phase bridge was simulated with sinusoidal phase currents, a symmetric 10 kHz carrier and a 50 Hz fundamental, taking the RMS of i_dc minus its average over one fundamental period. Sinusoidal PWM and centered space-vector modulation give the same RMS at every point in the table, and both match the formula to better than 0.01 %. Space-vector modulation still matches at M = 1.15, the end of its linear range.
- M = 0.5: φ = 0°, 30°, 60°
- simulation 0.6387, 0.5834, 0.4532 · I_N,rms
- M = 0.8: φ = 0°, 30°, 60°
- simulation 0.6186, 0.5849, 0.5109 · I_N,rms
- M = 1.0: φ = 0°, 30°, 60°
- simulation 0.5033, 0.5088, 0.5197 · I_N,rms
That close match is the ideal case, because the formula and the simulation make the same assumptions. The formula neglects AC-side current ripple and dead time, and the paper’s abstract reports agreement within about 8 % against simulation and measurement, which is a fair expectation for a real inverter.
Where the worst case is
At unity power factor the stress peaks at M = 0.61 with I_C,rms = 0.65·I_N,rms. That point is why “about 0.65 times the phase current” is a popular rule of thumb. At M = 1 it has fallen to 0.50. As cos φ drops, the peak moves to higher M and flattens: at cos φ = 0.9 it is 0.61 at M = 0.64, at 0.7 it is 0.55 at M = 0.74, and at 0.5 it is 0.52 at M = 0.98.
This matters for drives. A motor at rated torque and about 60 % speed runs near M = 0.6 with full current, so a bank sized only at the rated point (high M) can be undersized for the part of the speed range where it spends its time. Size for the full torque-speed envelope, and take the highest value. If you do not know the envelope, 0.65·I_N,rms is a safe limit.
Worked example
- 1U_dc = 400 V, I_N = 50 A rms (Î = 70.7 A), M = 0.8, cos φ = 0.9.
- 2The root evaluates to 0.593, so I_C,rms = 29.7 A. The simulation gives 29.66 A.
- 3Average DC current: (3/4)·0.8·70.7·0.9 = 38.2 A, or 15.3 kW. Check: 3·(113 V rms)·50 A·0.9 is the same 15.3 kW.
- 4With C = 100 µF and f_s = 10 kHz, the estimate I_C,rms/(2π·f_s·C) gives 4.7 V.
- 5The simulation shows 9.3 V peak-to-peak on average within a switching period, and 12 V at most. So here the estimate is low by a factor of 2 to 2.5 if you read it as peak-to-peak.
Use I_C,rms/(2π·f_s·C) for the order of magnitude only. It treats a pulse train as a single sine wave. Simulate the real waveform if ripple voltage is what limits the design.
Film or electrolytic
The two kinds fail the sizing in opposite ways. Film capacitors have very low ESR and carry large ripple per microfarad, so their size is often set by voltage ripple or ride-through. With an assumed 2 mΩ of ESR and 5.8 K/W, the 29.7 A above heats a film capacitor by about 10 K, which is easy. Electrolytics give far more capacitance per volume but carry much less ripple. With an assumed rating of 3 A per capacitor at this frequency, the same current needs about ten in parallel, and this is usually more capacitance than the design needed. These two figures are illustrative; use your datasheet values.
Electrolytics also bring voltage limits, since a 400 V link with margin usually needs 450 V or 500 V parts, or two lower-voltage parts in series with balancing. Life depends strongly on core temperature, so run the actual current split through the capacitor life calculator. Rated ripple must be corrected with the frequency multiplier from the datasheet. The bank also sets the inrush energy, which the precharge resistor calculator sizes for you. The heating calculation for the bank itself goes in the thermal calculator.
A DC source with its own ripple adds to this. A six-pulse diode rectifier adds current at 300 Hz or 360 Hz, which the inverter formula does not include. Because the frequencies differ, the two RMS values add as a root sum of squares. Check them separately against the electrolytic’s ratings, which differ between low and high frequency.
ESL and the busbar
The RMS calculation says nothing about the commutation loop. Each switching edge moves the full phase current between a device and the capacitor within tens of nanoseconds, and the loop inductance turns that into a voltage overshoot on the device. A large bank with a long connection can have the right RMS rating and still overstress the switches. A laminated busbar, low-ESL film capacitors near each half bridge, and paralleled parts all reduce this. A common arrangement is electrolytics for bulk energy with small film or ceramic capacitors right at the modules. In that case, watch for resonance between the two banks, and confirm how the current actually divides, in simulation or with a Rogowski coil, because the split is set by impedance and not by capacitance.
Sources
- J. W. Kolar, S. D. Round, "Analytical calculation of the RMS current stress on the DC-link capacitor of voltage-PWM converter systems," IEE Proc. Electr. Power Appl., vol. 153, no. 4, pp. 535–543, 2006.
This guide explains general engineering principles. Always verify your design with datasheets, simulation and measurement.