Damping an LC Filter: Sizing the R_d–C_d Leg

L and C exchange energy at f0 = 1/(2π√(LC)), and the only things removing that energy are resistances. Z0 = √(L/C) is the yardstick. A series resistance is small when it is well below Z0, and a parallel resistance is small in its effect when it is well above Z0.

Resonance and characteristic impedance

f0 = 1 / (2π√(LC)), Z0 = √(L/C)

Output filter with a resistive load

Q ≈ R_load / Z0

Series losses only

Q ≈ Z0 / (DCR + ESR)

Both together

1/Q ≈ Z0/R_load + (DCR + ESR)/Z0

Peak output impedance, undamped

|Z_o|,peak ≈ Q · Z0

Modern parts make this worse. Ceramic capacitors have milliohms of ESR and a good inductor has little DCR, so Q climbs as the filter improves. In the example, Z0 = 1 Ω and DCR + ESR = 30 mΩ, so Q = 33 with no load. A 1 Ω load would flatten this filter, and a 100 Ω load would barely touch it.

A tightly regulated converter draws constant power. If its input voltage rises, its input current falls, so within the loop bandwidth it looks like a negative resistance, R_in = −V²/P. At 12 V and 20 W that is −7.2 Ω. A negative resistance across the filter capacitor feeds energy into the resonance instead of removing it.

Here the positive damping is (DCR + ESR)/Z0 = 0.03, and the negative part is Z0/|R_in| = 0.139. The net is negative, so the filter is an oscillator. In a time-domain simulation of this linear circuit, a small disturbance grows about ninefold from one 0.4 ms window to the next.

Middlebrook put this as an impedance rule in 1976: adding an input filter leaves the loop gain almost unchanged if the filter output impedance stays well below the converter input impedance at every frequency. Formally the comparison uses two converter impedances, Z_N and Z_D, because the open-loop input impedance also matters. For a first check, |Z_o| against |R_in| shows the problem. This one fails by a factor of about 4.6 at the peak, since 33 Ω is far above 7.2 Ω.

Negative input resistance only holds below the crossover of the regulator. Above it, the input impedance follows the open-loop power stage. Check the real |Z_in| curve, by simulation or injection, before you trust a margin taken from the constant-power line.

Adding a plain resistor across C would burn power from the DC voltage. Putting a blocking capacitor C_d in series with it keeps the DC out while leaving the resistor active at f0. The choice is then a capacitor ratio n = C_d/C, and a single best R_d follows from it. Too small an R_d and C_d just adds to C, leaving a new undamped resonance at a lower frequency. Too large and the leg disconnects, leaving the original peak. The optimum sits between these.

Capacitor ratio

C_d = n · C

Optimal resistor

R_d,opt = Z0 · √( (2 + n)(4 + 3n) / (2n²(4 + n)) )

Resulting peak

|Z_o|,peak = Z0 · √(2(2 + n)) / n

These are the Erickson results for this circuit. A numerical sweep of |Z_o(f)| with no DCR or ESR agrees with the peak formula within 0.0001 % at n = 1, 2, 4 and 8.

n = 1

R_d = 1.449·Z0, peak = 2.449·Z0

n = 2

R_d = 0.913·Z0, peak = 1.414·Z0

n = 4

R_d = 0.612·Z0, peak = 0.866·Z0

n = 8

R_d = 0.427·Z0, peak = 0.559·Z0

Move the sliders and two things show up. Going from n = 4 to n = 8 doubles the capacitance and only lowers the peak by a third, so the returns fall off quickly. And R_d is forgiving at the optimum but not flat: at n = 4, half the optimal R_d gives a 1.18·Z0 peak and double gives 1.29·Z0, both still far better than no damping at all.

1. 1L = 10 µH, C = 10 µF gives Z0 = 1 Ω and f0 = 15.9 kHz. With DCR = 20 mΩ and ESR = 10 mΩ, Q = 33 and the peak is 33.3 Ω.
2. 2The converter draws 20 W at 12 V, so |R_in| = 7.2 Ω. Aim for a peak well below that; a factor of about 8 here gives a comfortable margin.
3. 3Take n = 4. Then C_d = 40 µF and R_d = 0.612 Ω. Use 0.62 Ω if you want a standard E96 value.
4. 4The formula gives a 0.866 Ω peak. With the DCR and ESR included, the numerical sweep gives 0.824 Ω, a little lower, because those resistances also help.
5. 5Check by simulation: the same disturbance that grew with no damping decayed by more than four orders of magnitude between the same two windows.
6. 6Check the resistor. At 200 kHz, C has about 0.08 Ω of reactance against 0.61 Ω in the leg, so only about 13 % of the ripple current enters it. For 1 A rms of ripple that is about 0.13 A rms and 10 mW. Start-up surges into C_d are often the larger stress.

C_d does not need low ESR or a tight tolerance, so it is usually the cheap electrolytic or polymer part, and the part you might have fitted anyway. If its ESR is close to R_d you can skip the separate resistor, but electrolytic ESR moves a lot with temperature and age. Use the worst-case ESR, and check the ripple current and lifetime in the capacitor life calculator. Remember that the bank must also survive the inrush, and that C_d adds to total capacitance for precharge purposes.

Keep the leg physically close to C. Its inductance sits in series with R_d, and it matters little at 16 kHz, but a long loop reduces the benefit at higher resonant frequencies. Ceramic capacitors lose capacitance with DC bias, so use the derated C when you compute Z0 and n, or the real optimum moves away from your design.

When a large C_d is not acceptable, a resistor in series with a second inductor L_b can sit in parallel with L. The inductor L_b blocks the resistor at high frequency, so attenuation near the switching frequency drops less than with a plain resistor, though it still degrades somewhat, because L_b now conducts in parallel with L. In a numerical sweep of the example, L_b = L/4 = 2.5 µH with about 0.61 Ω gives the same 0.866 Ω peak as n = 4. The price is a second magnetic part, and a split of the DC current between L and L_b according to their resistances.

• Designing the filter for attenuation alone and never plotting |Z_o|. The attenuation curve can look fine while the impedance peak breaks the loop.
• Testing at light load only. Negative resistance is strongest at full load and minimum input voltage, because |R_in| = V²/P is smallest there.
• Trusting the ESR of a ceramic capacitor to damp anything. At a few milliohms against Z0 of an ohm, it does almost nothing.
• Treating a stable bench result as proof. Low input line, cold electrolytics and a shorter source cable all shift the margin.

• R. W. Erickson, "Optimal single resistor damping of input filters," Proc. IEEE APEC 1999, pp. 1073–1079.
• R. D. Middlebrook, "Input filter considerations in design and application of switching regulators," IEEE IAS Annual Meeting, 1976.
• R. W. Erickson, D. Maksimović, "Fundamentals of Power Electronics," 2nd ed., Kluwer, 2001, ch. 10.