Synchronous Rectifier Timing in LLC Converters

Take a 12 V, 40 A output with a center-tapped secondary and 1.5 mΩ MOSFETs. At 100 kHz resonance the half-sine peak is about 63 A, so the channel drop at the peak is around 95 mV. The body diode of the same MOSFET drops roughly 0.7 V. Every nanosecond of diode conduction costs about seven times what the same nanosecond costs in the channel, and the diode also stores charge that has to be recovered when the opposite rectifier starts conducting.

Late turn-off is a different failure. Once the current reaches zero with the channel still on, nothing stops it from reversing: the output capacitor drives current back into the transformer. That current adds conduction loss, it upsets the primary-side current the converter relies on for soft switching, and it is interrupted abruptly when the gate finally goes low, which shows up as extra ringing on the drain.

• Below resonance (f_s < f_r): the secondary current finishes a half-sine at roughly the resonant period and returns to zero on its own, before the primary switches change state. For the rest of the half period only magnetizing current circulates on the primary side and the secondary is idle. The SR has to follow the current, not the primary gate signal.
• At resonance: the half-sine ends right at the primary switching edge. Both approaches agree, which is why this point is the easy case.
• Above resonance (f_s > f_r): the primary switches flip before the half-sine is complete. The secondary current is forced down through the leakage inductance in a short commutation interval with a steep slope. The SR has to turn off quickly, within tens of nanoseconds, or reverse current builds up.

A converter that regulates over a wide input or load range usually visits both regions. That rules out the oldest trick, deriving the SR gates from the primary gate signals with a fixed delay: it works above resonance, but below resonance the current ends before the primary edge, and the SR conducts backwards for the rest of the half period. It is still used, with extra logic, in some digitally controlled designs where the controller knows the operating point.

• Current sensing: a current transformer in the secondary path tells the controller directly when the current reaches zero. It is accurate, but at tens of amps the sensor adds loss and board area, and the small currents at light load are hard to resolve.
• Prediction: a digital controller estimates the conduction time from the switching frequency, the resonant components and the load. It is good in steady state and needs a reliable model and fall-back behaviour for transients.
• Drain-source voltage sensing: the controller watches V_DS of each SR and turns it off when the channel drop approaches zero. This is what most dedicated SR controller ICs do, because it needs no extra power components. It is also where most of the practical trouble comes from.

The controller does not measure the voltage across the die. It measures between its drain and source pins, and between those pins and the silicon sits some inductance: bond wires, the lead frame and any copper that is shared with the power path. While the current is falling, that inductance adds a voltage that makes the drain look less negative than the channel really is.

Voltage at the controller pins while the channel conducts

v_sensed = −(i_SR · R_ds(on) + L_s · di_SR/dt)

Slope near the end of a half-sine

|di/dt| ≈ I_pk · 2π · f_r

Threshold that would turn off at zero current

V_th,off ≈ L_s · |di/dt| at the zero crossing

With the numbers above, the slope at the end of the half-sine is about 40 A/µs. Each nanohenry in the sense path is then worth 40 mV, more than the entire channel drop during the last 15 % or so of the conduction interval. The UCC24624 datasheet puts typical package inductance at 2 to 10 nH. A comparator set to a few millivolts above zero sees its threshold crossed well before the current is anywhere near zero, the gate drops early, and the body diode carries the tail.

Raising the threshold to cancel the inductive term helps, but only at one operating point. The slope depends on the peak current, which follows the load, and above resonance it is set by the commutation instead of the half-sine. A threshold that is right at full load is too high at light load, and then the SR turns off late and conducts backwards.

The waveform is simplified. Below resonance the current is a half-sine at f_r; above resonance it is cut at T_s/2 and falls with the commutation slope you enter. The gate turns on 150 ns after conduction starts and turns off 25 ns after the sensed voltage crosses the threshold; below resonance and at resonance it is forced off at the end of the half period, as a two-channel interlock would do. Magnetizing current, C_oss ringing, proportional gate drive and minimum on-time are left out. Use it to see the trends, not to set a threshold for a real board.

Start with the defaults: f_s at 0.9 of resonance, 40 A, 1.5 mΩ and 1.5 nH, which is already below the package range quoted above. The gate drops about 0.7 µs before the current reaches zero. The diode tail adds roughly 0.76 W per rectifier on top of 1.6 W of channel loss, so the pair loses about 45 % more than it would with perfect timing.

• Set L_s to 0. The early turn-off disappears and is replaced by a small reverse current, because a positive 10.5 mV threshold with 1.5 mΩ is only crossed after the current has reversed by about 7 A.
• Put L_s back to 1.5 nH and set the threshold to the value shown under "Threshold for zero-current turn-off" (about 64 mV). The diode tail practically disappears.
• Keep that threshold and drop the load to 10 A. The ideal value falls to about 16 mV, the SR now stays on past zero, and reverse current flows until the end of the half period.
• Move the slider above 1.0. The required threshold jumps to roughly L_s times the commutation slope (150 mV at 1.5 nH and 100 A/µs) because the current is now ended by the primary switches. Above resonance, turn-off speed matters more than the threshold.

The commercial parts take different routes to the same problem. The figures below are the typical values from each document; check the current revision of the datasheet before relying on any of them.

• TI UCC24624: turns on when V_DS falls below −265 mV and off when it rises above +10.5 mV, with a 23 ns typical turn-off delay. During conduction it lowers the gate voltage so that V_DS is regulated to about −35 mV (proportional gate drive), which keeps the gate close to its threshold when the turn-off command arrives. A resistor on the VSS pin, fed by an internal 330 µA source, raises only the turn-off threshold to cancel package inductance; the datasheet recommends keeping that offset below 70 mV and says low-inductance packages such as SON 5×6 do not need it.
• onsemi FAN6248 (application note AND9618): uses an adaptive "virtual" turn-off threshold. The controller shifts the threshold from cycle to cycle, in steps set by an external offset resistor, so that the L·di/dt offset is cancelled as the load changes. The note explains that because di/dt changes with load, the effective dead time also changes with load.
• ST SRK2001 (application note AN4674): moves the turn-off instant cycle by cycle to minimise the remaining body-diode conduction, with no external component for the stray inductance. A second, faster comparator with its own adaptive threshold handles load steps and above-resonance operation, and the driver stops below 60 % of the resonant frequency to avoid current inversion.

Academic work has gone further. Fu, Liu, Lee and Xu (2009) proposed a driving scheme that compensates the package-inductance voltage with a network of resistors, capacitors and switches and reported almost no body-diode conduction; later papers point out that this kind of RC compensation needs a fairly accurate value of the parasitic inductance.

Turn-on is easier but not free. The controller waits until the body diode starts conducting, which pulls V_DS well below the turn-on threshold, then needs a delay of the order of 100 to 200 ns before the gate is fully up. That interval is diode conduction too, and at high switching frequency it is a noticeable fraction of the half period.

• Ringing after turn-on can look like a turn-off condition. Controllers blank the turn-off comparator for a minimum on-time; the UCC24624 uses a fixed 475 ns, and the FAN6248 uses a fraction of the previous conduction time.
• At light load the conduction time can become shorter than a fixed minimum on-time, and the SR is then held on into reverse current. Adaptive minimum on-time exists for this reason.
• Capacitive current spikes, mainly below resonance and in burst mode, can pull V_DS negative without real load current. The UCC24624 lengthens its turn-on delay from 155 ns to 275 ns when it detects burst operation or very short conduction, and the FAN6248 detects current inversion and lengthens its delay until a number of clean cycles have passed.

• Route the drain and source sense lines from the MOSFET pads themselves, not from a point on the power copper. TI recommends running the VD and VSS traces directly to the MOSFET pads. For D-PAK and D2-PAK parts, the onsemi note suggests sensing at the edge of the drain pad near the source or gate pin.
• Prefer packages with low internal inductance and a Kelvin source pin. The less inductance sits inside the sense loop, the less threshold correction you need and the less it varies with load.
• Keep the gate loop short and the gate pull-down strong. A fast turn-off command is wasted if the gate charge drains slowly; for higher-power designs the onsemi note adds a PNP discharge stage.
• Check the SR timing with [the LLC design tool](/tools/llc-design) operating points in hand: minimum and maximum input voltage at full load usually give the deepest below-resonance and the highest above-resonance operation.

1. 1Probe V_DS of one SR together with its gate. Diode conduction shows up as a step to about −0.7 V just after the gate falls or just before it rises.
2. 2Repeat at the corners: full and light load, minimum and maximum input voltage, start-up and any burst mode. The worst case for early turn-off and the worst case for reverse current are usually at different corners.
3. 3Look for reverse current as a positive drain voltage spike right after the gate falls, or measure the transformer secondary current with a Rogowski coil if the layout allows it.
4. 4Compare SR temperatures and efficiency with the threshold offset changed by a few steps. If the diode tail is a large part of the loss, the [MOSFET loss calculator](/tools/mosfet-loss) will show how little a lower R_ds(on) buys you until the timing is fixed.

• Texas Instruments, "UCC24624 Dual-Channel Synchronous Rectifier Controller for LLC Resonant Converters," datasheet SLUSD48C, July 2018, revised March 2022.
• onsemi, "LLC Resonant Converter Synchronous Rectification Design using FAN6248," application note AND9618/D, Rev. 2, January 2018.
• STMicroelectronics, "SRK2001 adaptive synchronous rectification controller for LLC resonant converter: evaluation board family," application note AN4674.
• D. Fu, Y. Liu, F. C. Lee, M. Xu, "A Novel Driving Scheme for Synchronous Rectifiers in LLC Resonant Converters," IEEE Transactions on Power Electronics, vol. 24, no. 5, pp. 1321–1329, May 2009.
• Z. Luo, Z. Wu, X. Quan, X. Xie, X. Dou, Q. Hu, "Synchronous rectification of LLC resonant converters based on resonant inductor voltage," Frontiers in Energy Research, vol. 11, 2023.