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Sliding-Mode Control for DC-DC Converters

By the Power Electronics Hub editor · Published 2026-11-01

A switching converter already behaves like the relay that sliding-mode theory is built around: the switch is either on or off, and the plant has a different set of equations in each position. Sliding-mode control takes that literally. Instead of averaging the switch into a duty cycle and designing a linear compensator, it defines a line in the state space and switches whenever the state crosses it. The idea is old and the theory is clean. The practical questions are what to put in the surface, what happens far from the operating point, and what the switching frequency ends up being.

The surface for a buck converter

Take a synchronous buck with inductor L, output capacitor C and load R. Use the voltage error as the first state and its time derivative as the second. The derivative of the error is just the capacitor current with a sign and a scale, so it can be measured instead of computed.

Voltage error
x1 = V_ref − v_o
Its derivative
x2 = dx1/dt = −i_C / C = v_o/(R·C) − i_L/C
Sliding surface
s = α·x1 + x2
Switching law
u = 1 when s > 0, u = 0 when s < 0

If the state stays on s = 0, then dx1/dt = −α·x1 and the error decays exponentially with time constant 1/α. The converter parameters do not appear in that equation. This is the property people usually quote: on the surface, the response is set by the controller alone, not by L, C or the load. It only holds while the state actually stays on the surface, which is the next question.

The sign of the switching law is easy to check. When s is positive the output is low or falling, turning the switch on raises the inductor current, the capacitor current rises, x2 falls and s comes back down.

Reaching the surface and staying on it

Two things have to be true. From anywhere the converter can start, the state must move towards the surface (the reaching condition). Once there, both switch positions must push s back towards zero from either side (the existence condition). Differentiating s along the buck equations gives a compact way to write the second one.

Rate of change of s
ds/dt = (α − 1/(R·C))·x2 − (u·V_in − v_o)/(L·C)
Equivalent control (ds/dt = 0)
u_eq = [ v_o + L·C·(α − 1/(R·C))·x2 ] / V_in
Sliding exists where
0 < u_eq < 1

Near the operating point x2 is close to zero and u_eq is close to V_o/V_in, the ordinary duty cycle, so sliding exists as long as V_ref is between zero and V_in. Far from it, at start-up for example, x2 can be large and u_eq can leave the 0 to 1 range. The state then overshoots the surface, the switch stays in one position for a long time, and the inductor current climbs without anything in the control law limiting it. A large α makes the surface steep and makes this worse. Real designs either clamp the reference with a soft-start ramp, add a current limit, or both.

Try it: start-up and a load step

The simulation starts a synchronous buck from zero, lets it settle, then halves the load resistance in the middle of the run. The upper plot shows the start-up trajectory in the (x1, x2) plane with the surface drawn as a dashed line. The lower plot shows output voltage and inductor current over time. Try a large α (50000 or more) to watch the trajectory miss the surface at start-up, and switch between the two implementations to compare their switching frequency.

Switching frequency, full / double load128 / 128 kHz (estimate 128)Average v_o, full / double load11.97 / 12.00 VTime constant on the surface 1/α200 µsPeak i_L at start-up6.4 Av_o minimum after load step11.90 V

Start-up trajectory in the phase plane

Start-up and load step

Model: ideal switches, synchronous rectification, no ESR, no DCR, no sensing delay and no current limit, integrated with a fixed 10 ns step. The PWM mode uses u_eq plus a reaching term λ·s with λ fixed internally; it is an illustration of the idea, not the exact controller from the references. Real hardware has delays and parasitics that this model leaves out, so treat the numbers as trends.

Hysteresis: the frequency follows the input voltage

An ideal sliding controller would switch infinitely fast. A real one adds a hysteresis band ±κ around s = 0, and the band sets the switching frequency. Close to steady state the α·x1 term is small compared with x2, so the band is almost entirely capacitor current, which means it is almost entirely inductor ripple.

Ripple set by the band
ΔI_L ≈ 2·κ·C
Switching frequency
f_sw ≈ V_o·(1 − V_o/V_in) / (L·ΔI_L)

With the chart defaults (24 V to 12 V, 47 µH, ΔI = 1 A) this gives about 128 kHz, and the simulation lands within a few percent of it. Change V_in to 36 V and the estimate rises to about 170 kHz; at 18 V it falls to about 85 kHz. Change the load and very little happens, which is a nice property in CCM. The input voltage dependence is the part that hurts, because the input filter, the magnetics and the EMI margin are all designed around a frequency that now moves by a factor of two over the input range.

The usual fix follows straight from the formula: make the band a function of the measured V_in and V_o so that the computed frequency stays constant. That is the adaptive hysteresis band. It brings the frequency back under control in steady state, but during transients the frequency still moves, and the band calculation now depends on the value of L.

What chattering means in a converter

In mechanical systems, chattering is a nuisance that comes from the discontinuous control and has to be suppressed. In a converter the discontinuity is the switch itself, so the "chattering" is simply the switching ripple and cannot be removed. What can go wrong is that the ripple becomes larger and less regular than the band suggests.

  • Delay. The comparator, gate driver and switch take time to respond, so s overshoots the band on every edge. The ripple gets bigger and the frequency drops below the formula, more so at high frequency where the delay is a larger fraction of the period.
  • Noise on x2. Differentiating the output voltage amplifies switching noise. Measuring the capacitor current directly (a sense resistor in series with C, or a current transformer) is cleaner. With an electrolytic or polymer output capacitor, the ripple across the ESR already looks like the capacitor current, which is why hysteretic ripple regulators work without a separate sense.
  • Comparator bounce. Without enough hysteresis, ringing after each edge crosses the threshold again and causes multiple transitions. Blanking after each edge helps.

Equivalent control and fixed-frequency PWM

The equivalent control u_eq is the duty cycle that keeps ds/dt at zero on average. Feeding it to an ordinary PWM modulator turns the sliding controller into a fixed-frequency controller with the sliding surface built into its gains. Tan, Lai and Tse developed this approach in detail for the buck, boost and buck-boost, with design equations for the gains and the existence conditions in PWM form.

On its own, u_eq only holds s where it already is; it does not pull the state onto the surface. The chart adds a reaching term λ·s for that, so the averaged s decays at a rate set by λ. With that in place, the controller behaves much like a state-feedback controller on the output voltage and capacitor current. That is not a coincidence: the surface s = α·x1 + x2 is a proportional-derivative combination of the error, and averaging the switch takes away most of what made the controller nonlinear.

One trap is easy to fall into in a digital implementation. If x2 is sampled once per period at the turn-on edge, it is always sampled at the bottom of the inductor ripple. The sample is then offset by half the ripple divided by C, and the loop settles with a voltage error of about ΔI/(2·C·α). With the chart defaults at 100 kHz that is more than a volt. The chart averages x2 over the previous period, which removes the offset; sampling at the middle of the on-time does the same job.

Boost and buck-boost converters

The buck is the friendly case because the switch drives the output through the inductor and capacitor without anything in between. In a boost or buck-boost, raising the duty cycle first takes energy away from the output before it delivers more. That is the right-half-plane zero of the averaged model, and it means a surface built only from the output voltage error and its derivative gives unstable motion on the surface.

  • Slide on the inductor current instead: s = i_L − I_ref, with I_ref produced by a slower outer voltage loop. The fast loop behaves like peak or average current-mode control, and the outer loop is designed with ordinary linear tools.
  • Or include more states. Tan, Lai and Tse use the voltage error, its derivative and its integral for the boost in their PWM-based design. The integral removes the steady-state error that the finite band and the non-ideal components leave behind.
  • Either way, check the existence condition over the full input and load range. For the boost it is more restrictive than for the buck, and it is the first thing to fail at light load or at input-voltage extremes.

When it is worth using

Sliding-mode voltage control gives a fast large-signal response that does not depend much on the load, and the hysteresis version needs very little hardware: a few sensed signals, a summing node and a comparator. That is why it shows up in point-of-load converters and in hysteretic regulator ICs. The costs are a switching frequency that moves unless something holds it, a sensitivity to sensing delay and noise, and a design that is harder to describe with the Bode plots most reviewers expect.

If the converter is already digitally controlled at a fixed frequency, the PWM form with an equivalent-control term is usually the easier path, and it can be compared directly with a Type II or Type III compensator designed the classical way. The buck voltage-loop lab shows the linear alternative on the same kind of plant.

  1. 1Start with α well below the LC resonant angular frequency times a few, and well below the switching angular frequency. With the defaults here, the LC resonance is near 2.3 kHz, and α = 5000 s⁻¹ gives a 200 µs time constant.
  2. 2Choose the band from the ripple you want, then check the frequency at minimum and maximum V_in with the formula above.
  3. 3Simulate start-up and short-circuit recovery with the real current limit in place. That is where the reaching phase lives.
  4. 4On the bench, look at the comparator output alongside the switch node. Extra edges or a frequency well below the formula point to delay or noise in the x2 path.

Sources

  • V. I. Utkin, "Variable structure systems with sliding modes," IEEE Transactions on Automatic Control, vol. AC-22, no. 2, pp. 212–222, April 1977.
  • R. Venkataramanan, A. Sabanovic, S. Ćuk, "Sliding mode control of DC-to-DC converters," Proc. IEEE IECON, 1985.
  • S.-C. Tan, Y.-M. Lai, C. K. Tse, M. K. H. Cheung, "On the practical design of a sliding mode voltage controlled buck converter," IEEE Transactions on Power Electronics, vol. 20, no. 2, 2005.
  • S.-C. Tan, Y.-M. Lai, C. K. Tse, "A unified approach to the design of PWM-based sliding-mode voltage controllers for basic DC-DC converters in continuous conduction mode," IEEE Transactions on Circuits and Systems I, vol. 53, no. 8, 2006.
  • S.-C. Tan, Y.-M. Lai, C. K. Tse, Sliding Mode Control of Switching Power Converters: Techniques and Implementation, CRC Press.

This guide explains general engineering principles. Always verify your design with datasheets, simulation and measurement.

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