What the model contains
The plant is the state-space average of a CCM buck: L·di_L/dt = d·V_in − v_out − i_L·R_L and C·dv_C/dt = i_L − i_load, with the output voltage taken across the capacitor and its ESR. The equations are integrated with a fourth-order Runge–Kutta step, eight steps per switching period. Switching ripple is not present; what you see is the average over each period, which is what the controller samples anyway.
The controller samples v_out once per period, computes u = Kp·e + Ki·∫e + Kd·d(−v_out)/dt with a first-order filter on the derivative, divides by the 1 V PWM ramp and clamps the duty cycle to 0 … 0.95. The result takes effect in the next period. That one-sample delay plus the zero-order hold of the PWM is the 1.5·T_s shown under the loop data, and it is the main reason the usable crossover frequency is a fraction of f_s.
With the default 4.7 µH and 100 µF the LC resonance sits at 7.3 kHz with a Q of about 5.7 at 3 A. A plain PI cannot stabilize a crossover above that resonance: the plant already contributes nearly 180° of lag there, and the integrator adds 90° more. The derivative term is what provides the phase lead, which is the same job the two zeros of a Type III compensator do. Set Kd to zero and move Kp down until the loop is stable again to see the price in bandwidth.
Reading the phase margin from the ringing
The presets place two controller zeros one sixth of the crossover frequency below it and then search for the crossover frequency that gives the target margin. Compare the load-step recovery of the 55° and 25° presets: the 25° case overshoots the reference on the way back and rings for several cycles at roughly the crossover frequency. The number of visible cycles grows as the margin shrinks; near 0° the oscillation no longer decays, and the duty cycle starts hitting its limits, which is the bounded oscillation you get instead of a clean exponential blow-up.
The gain margin matters as much here. Raising Kp and Ki together with Kd fixed moves the crossover up into the region where the delay dominates the phase, so the gain margin collapses before the phase margin does. Raising f_s shrinks the delay and lets the same gains recover their margin, which is the quantitative argument for a faster switching frequency in a voltage-mode design.
What the model leaves out
The averaged model is valid while the inductor current stays positive. A diode-rectified buck enters discontinuous conduction when the valley current reaches zero; a synchronous one with forced continuous conduction does not, but its losses change. The page flags the moment the simulated current goes negative so you know the result past that point is only indicative. Switching ripple, ADC quantization, the gate-driver dead time, the current limit and the slope of a real soft-start circuit are all absent.
Treat the gains as dimensionless controller settings rather than firmware constants. To turn them into fixed-point coefficients for a specific sampling frequency, use the PI discretization calculator; to design the Type III network that implements the same lead in an analog loop, use the compensator calculator. Both are linked below.
Sources
R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics, 3rd ed., Springer, 2020, chapters 7 and 9 (averaged converter models, voltage-mode loop design).
G. F. Franklin, J. D. Powell and M. L. Workman, Digital Control of Dynamic Systems, 3rd ed., Addison-Wesley, 1998 (zero-order hold and computation delay in sampled loops).
H. D. Venable, "The K factor: a new mathematical tool for stability analysis and synthesis," Proc. Powercon 10, 1983 (zero placement for Type II / III compensation).
The animation follows the equations stated on this page. Conventions differ between textbooks and software libraries; check the one your code uses before comparing numbers.