PWM, ADC and Interrupt Timing, Animated

Center-aligned PWM and where to sample

In up-down counting the counter rises from zero to the period value and falls back again, so each PWM period has two natural events: the valley, where the counter is zero, and the peak, where it equals the period. With the high-side switch on while the counter is above the compare value, the on-time is centered on the peak and the off-time on the valley.

The inductor current is a triangle whose midpoints fall exactly at the centers of the on-time and the off-time. Sampling at the valley or the peak therefore returns the average current of the period without any filtering, which is why these two events are the usual ADC triggers. Move the trigger delay away from zero and the sample picks up part of the ripple: with the defaults, each microsecond of delay at the valley costs 0.2 A on a 4 A ripple.

Acquisition, ringing and the low-side shunt

The ADC's sample-and-hold needs an acquisition window, and the signal must be settled throughout it. Each switching edge, including the edge of the complementary switch after the dead time, excites ringing in the power loop and the current sensor. If the window falls inside that ringing, the converted value depends on where in the oscillation it landed. The animation draws the ringing slower than real so that it is visible; only its settling time enters the check.

A shunt in the low-side source carries the phase current only while the high-side switch is off. Sampling at the valley then works only while the off-time leaves room for dead time, settling and acquisition, which limits the duty cycle: D_max = 1 − 2·(t_dead + max(t_settle − t_delay, t_delay + t_acq))/T_s. With the defaults (20 kHz, 0.5 µs dead time, 1.5 µs settling, 0.5 µs acquisition), D_max is 92 %. A common workaround in three-shunt drives is to skip the phase with the shortest window and reconstruct it from the other two.

From conversion to new duty: where the delay comes from

After conversion the ADC raises an end-of-conversion interrupt, the control law runs, and the new compare value is written. The timer does not use it straight away. Compare registers are shadowed and copied to the active register only at selected counter events, so that a write in the middle of a period cannot produce a glitch or a missing pulse.

With the sample at the valley and the shadow loaded only at the valley, the new duty takes effect one full period after the sample: 49.5 µs, or 0.99 T_s, with the defaults. Loading at both valley and peak cuts this to about half a period, provided the interrupt finishes before the peak; if it does not, the update slips to the next valley. If the interrupt is still running when the next sample is due, the loop is overrunning and the timing no longer holds.

For loop design, this path is often modelled as the computation delay, up to one period here, plus roughly half a period for the PWM update itself. That delay, rather than the converter, is usually what limits the crossover frequency of a digital current loop.

How two common MCU families express this

TI C2000 ePWM: the time base generates CTR = Zero and CTR = PRD events, and in up-down count mode the period is 2·TBPRD·T_TBCLK. The event-trigger submodule turns a selected event into the ADC start-of-conversion signal SOCA or SOCB; the selection in ETSEL[SOCASEL] includes CTR = Zero and CTR = PRD. Compare registers are shadowed, and the shadow-to-active load can take place at CTR = Zero, at CTR = PRD or at both (CMPCTL[LOADAMODE]). Sources: TMS320F2837xD Technical Reference Manual (SPRUHM8), ePWM chapter, and the TMS320x28xx/28xxx ePWM module reference guide (SPRU791). Which options a particular device offers is listed in its own TRM.

STM32 timers: in center-aligned mode the update event is generated on both overflow and underflow, and buffered registers such as ARR, PSC and CCRx are loaded with their preload values at the update event; the repetition counter can lower the update rate. The trigger output TRGO is selected with the MMS bits in TIMx_CR2, for example the update event or an OCxREF signal, and advanced-control timers on series such as STM32G4 add TRGO2 for timer and ADC synchronization. Source: ST application note AN4013, Introduction to timers for STM32 MCUs. How the ADC selects a timer trigger for regular and injected conversions differs between ADC versions, and we have not verified the field names for every series, so take them from the ADC chapter of your device's reference manual.

Checking it on the bench

Set a spare GPIO high at the start of the interrupt and low at the end, and scope it together with the PWM output and the current sensor signal. One capture then shows the real sample instant, the interrupt length and the margin before the next sample, which is the quickest way to confirm that the configuration does what the timing diagram intends.