How it works
An average-current-mode PFC runs two loops at very different speeds. The inner current loop forces the inductor current to follow a sinusoidal reference, so it needs bandwidth in the kilohertz range. The outer voltage loop sets the amplitude of that reference to hold V_out, and it must be slow, because the output capacitor carries an unavoidable ripple at twice the line frequency.
The model follows Todd's UC3854 application note (Unitrode U-134, TI SLUA144), averaged and linearized at the line peak. Between the L–C_o resonance and the switching frequency the boost stage looks like an integrator from the current-amplifier output to the sensed current, V_out·R_s/(V_s·s·L). U-134 also limits the current amplifier's mid-band gain so that the amplified inductor down-slope never exceeds the PWM ramp slope; at that limit the crossover lands at f_s/(2π).
For the voltage loop, the multiplier, squarer and divider turn the voltage-amplifier output into a power command: a swing of ΔV_vea spans zero to full input power. With a constant-power load (a downstream DC-DC stage) the plant is an integrator, P_in/(ΔV_vea·V_out·s·C_o), exactly as in U-134. A resistive load adds a pole at 2/(R·C_o).
Both compensators here are op-amp Type II networks sized with Venable's k factor for the target crossover and phase margin, then rounded to standard parts. The output ripple V_o,pk = P_in/(2π·2f_line·C_o·V_out) passes through the voltage amplifier; the part that remains on V_vea modulates the current reference, and U-134 gives about half of that percentage as third-harmonic input current. In the Type II formulas G_c is the mid-band gain the compensator needs, G_c = 1/|G(j·2π·f_c)|, so that the loop magnitude is 1 at f_c.
Design procedure
- 1Enter the power stage and the controller constants: the ramp amplitude V_s and the voltage-amplifier output range ΔV_vea from the controller datasheet.
- 2Pick the current-loop crossover, around f_s/10, and check that the computed mid-band gain stays below the slope limit.
- 3Pick the voltage-loop crossover, usually around 10 Hz and below f_line/4, and a phase margin of 45° to 60°.
- 4Read the 2·f_line ripple on the voltage-amplifier output and the third-harmonic estimate. If it is too high, lower the voltage-loop crossover or increase C_o.
- 5Check the margins with the rounded parts, at both line frequencies and, if the load type is uncertain, for both load models.
Formulas
- Current-loop plant
- V_rs / V_cea = V_out·R_s / (V_s·s·L)
- Current-amplifier slope limit
- G_ca,max = V_s·L·f_s / (V_out·R_s), f_ci at that gain = V_out·R_s·G_ca / (2π·L·V_s) = f_s/(2π)
- Voltage-loop plant (power balance)
- V_out / V_vea = P_in / (ΔV_vea·V_out·s·C_o) (constant-power load); (P_in/(ΔV_vea·V_out))·R/(2 + s·R·C_o), R = V_out²/P_out (resistive load)
- Type II by the k factor
- boost = PM − 90° − ∠G(j·2π·f_c), G_c = 1/|G(j·2π·f_c)|, k = tan(boost/2 + 45°); C2 = 1/(k·ω_c·R1·G_c), C1 = C2·(k² − 1), R2 = k/(ω_c·C1)
- Second-harmonic ripple
- V_o,pk = P_in / (2π·2f_line·C_o·V_out), V_vea,pk = V_o,pk·|Gc(j·2π·2f_line)|
- Third harmonic from output ripple
- third harmonic ≈ ½ · (V_vea,pk / ΔV_vea) · 100 %
Worked example
With the U-134 defaults (400 V, 250 W, 100 kHz, 1 mH, 450 µF, R_s = 0.25 Ω, V_s = 5.2 V, ΔV_vea = 4 V, 60 Hz), the slope limit allows a current-amplifier gain of 5.2. A 10 kHz current loop with 60° margin needs k = 3.73; with R_ci = 3.9 kΩ the standard parts are R2 = 13 kΩ, C1 = 4.7 nF and C2 = 330 pF, giving 9.60 kHz and 61.2°, and the mid-band gain of 3.33 stays below the limit. For the voltage loop at 10 Hz and 45° (k = 2.41, R_vi = 511 kΩ) the parts are 110 kΩ, 330 nF and 68 nF, giving 10.0 Hz and 45.0°. The output ripple is 1.84 V peak; the amplifier passes 0.0373 of it at 120 Hz, leaving 68.8 mV, or 1.72 % of ΔV_vea, which corresponds to roughly 0.86 % third harmonic.
Common mistakes
- Designing the voltage loop for fast transient response alone. A crossover near 2·f_line puts the output ripple straight into the input current.
- Ignoring the slope limit in the current amplifier. The loop looks stable in the average model but can break up near the line zero crossings.
- Forgetting that the voltage-loop gain scales with P_in. Without line feedforward the gain also changes with the square of the line voltage; the UC3854's squarer and divider remove that dependence.
- Treating the third-harmonic estimate as the whole distortion budget. Feedforward ripple, cusp distortion near the zero crossings and the input filter add to it.
Frequently asked questions
How does this compare with the U-134 example?
The defaults are that example. Its equations are reproduced: an amplifier gain of 5.2, f_ci of 15.9 kHz (15.7 kHz with R_cz rounded to 20 kΩ), C_cz ≈ 507 pF, V_o,pk = 1.84 V, G_va = 0.0326 and f_vi = 19.1 Hz. Running the full loops with the parts the note finally chose gives 17.5 kHz with 46.7° and 14.9 Hz with 52.5°, because the note's formulas are asymptotic.
Why must the voltage loop be so slow?
The output ripple at 2·f_line is part of normal operation. Whatever the voltage amplifier passes through at that frequency modulates the current reference and shows up as third-harmonic input current, so the loop has to cross over well below 2·f_line, typically around 10 Hz.
Why does the current amplifier have a gain limit?
The PWM comparator compares the amplified current signal with the ramp. If the amplified inductor down-slope is steeper than the ramp, the modulator can jump between states from cycle to cycle. U-134 sets the mid-band gain so the two slopes match at the worst case, when the input voltage is near zero.
Should I model the load as constant power or as a resistor?
A PFC usually feeds a DC-DC converter, which draws constant power; then the plant is a pure integrator, as in U-134. A resistive load adds damping through the pole at 2/(R·C_o), which slightly lowers the phase lag at low frequency.
Results are engineering estimates. Verify your design with datasheets, simulation and measurement.