How it works
A boost PFC shapes the input current into a sine in phase with the line while it charges a DC bus above the line peak. Because the input voltage sweeps from zero to its peak twice per line cycle, the duty cycle and the inductor ripple change continuously, and the worst case for each quantity sits at a different point of the cycle and of the input range.
Low line at full power sets the inductor: the current is highest there, and the ripple is fixed as a fraction r of the low-line peak current at the top of the sine. The same inductor is then checked at high line, where the ripple can be larger in absolute terms because v_in passes through V_out/2, but the line current is much smaller, so the current valley reaches zero near the zero crossings and the stage runs in discontinuous conduction there.
The output capacitor has two separate jobs. It must carry the output through a line dropout (hold-up), and it must keep the double-line-frequency ripple within limits, because a single-phase PFC delivers power pulsating at 2·f_line while the load draws constant power. Whichever requirement asks for more capacitance governs.
Switch, diode and capacitor RMS currents use the usual low-line approximations with M = 8√2·V_ac/(3π·V_out). M is not a voltage gain: it is the share of the squared input RMS current that the diode carries over a line cycle, so I_D,rms² = M·I_in,rms² and I_sw,rms² = (1 − M)·I_in,rms². These formulas ignore the high-frequency ripple; at the ripple ratios used here that changes the results by a few percent.
Design procedure
- 1Fix the input range, line frequency, output voltage and power, and an estimated efficiency. Check that the high-line peak stays well below V_out.
- 2Choose the switching frequency and the ripple ratio at the low-line peak, typically 20 % to 40 %, and compute the inductance.
- 3Check the inductor at both line extremes: the largest peak current, the largest ripple and the DCM fraction at high line. Specify the inductance at the peak current, not at zero bias.
- 4Size the output capacitor for hold-up and for 2·f_line ripple, take the larger value, and confirm the capacitor's RMS ripple-current rating against the computed value.
- 5Use the low-line RMS and average currents to select the switch, boost diode and bridge, and to estimate conduction losses.
Formulas
- Line current
- I_in,rms = P_out / (η·V_ac), I_pk = √2·I_in,rms
- Boost inductance
- L = V_pk,min·(1 − V_pk,min/V_out) / (f_s·r·I_pk,min)
- Ripple over the line cycle
- ΔI_L(θ) = v_in·(1 − v_in/V_out) / (f_s·L), v_in = V_pk·sin θ; max V_out/(4·f_s·L) at v_in = V_out/2
- Output capacitance
- C_hold = 2·P_out·t_hold / (V_out² − V_min²), C_ripple = P_out / (2π·f_line·ΔV_pp·V_out)
- Low-line current stress
- M = 8√2·V_ac / (3π·V_out): I_sw,rms = I_in,rms·√(1 − M), I_D,avg = P_out/V_out, I_D,rms = I_in,rms·√M
- Capacitor ripple, bridge loss, stored energy
- I_C,rms = √(I_D,rms² − I_o²), P_bridge = 2·V_f·(2√2/π)·I_in,rms, E = ½·L·I_peak²
Worked example
With the defaults (90–265 V, 50 Hz, 400 V, 1 kW, 95 %, 65 kHz, 30 % ripple), the low-line input current is 11.70 A rms and 16.54 A peak. The inductance comes out at 269 µH, giving 4.96 A of ripple at the low-line peak and a 19.02 A inductor peak that stores 48.7 mJ. At 265 V the largest ripple is 5.72 A p-p at 32.5°, where v_in ≈ V_out/2, and the stage is in DCM for about 34 % of each half cycle. Hold-up for 10 ms down to 300 V needs 286 µF, but 20 V p-p of 100 Hz ripple needs 398 µF, so ripple governs. At low line M = 0.270, the switch carries 9.99 A rms, the diode 2.50 A average and 6.08 A rms, the capacitor 5.54 A rms, and the bridge dissipates about 21 W with 1 V diodes.
Common mistakes
- Specifying inductance at zero bias. Powder cores lose a large part of their permeability at the peak current, so the real ripple at full load ends up well above the design value.
- Sizing the output capacitor for hold-up only and forgetting its ripple-current rating, which often decides the capacitor count in practice.
- Running V_out too close to the high-line peak. A 265 V line peaks at about 375 V, so a 400 V bus leaves only a small margin for line surges and for the controller to regulate.
- Using 60 Hz in the ripple calculation for a product sold worldwide. The 50 Hz case needs about 20 % more capacitance for the same ripple.
Frequently asked questions
Why is the inductor sized at low line?
The line current is largest at minimum input voltage and full power, so that is where a given ripple ratio translates into the largest peak current and where the CCM assumption matters most. The high-line check then shows how far the stage drifts into DCM.
Why can high line have more ripple than low line?
The ripple is largest where the instantaneous input equals half the output voltage, V_out/(4·f_s·L). A 90 V line peaks at 127 V and never reaches 200 V, while a 265 V line passes through 200 V twice per half cycle, so its absolute ripple is larger even though its current is smaller.
Should hold-up or ripple set the output capacitor?
Both have to be met. Hold-up depends on how far V_out may sag and for how long; ripple depends on line frequency and the allowed peak-to-peak voltage. With 50 Hz lines and tight ripple limits, ripple often governs; long hold-up times usually push the hold-up requirement above it.
How accurate are the RMS current formulas?
They assume a sinusoidal line current with no high-frequency ripple and CCM over the whole cycle. For ripple ratios around 20–40 % at low line the error is a few percent, which is fine for selecting parts; loss calculations for the final design should use simulated waveforms.
Results are engineering estimates. Verify your design with datasheets, simulation and measurement.