Measuring Dead Time and Shoot-Through Margin on a Real Gate Drive

The dead time that protects the leg is the interval between the outgoing switch's gate falling below its threshold voltage and the incoming switch's gate rising above its threshold. Measuring between the 50 % points of the driver outputs, or between the PWM edges at the controller, tells you about the logic path but not about the switches. The two gates also discharge and charge through different resistances when the board uses separate turn-on and turn-off resistors, so the delay to threshold is different for the two edges.

Use the threshold at the hottest junction temperature you expect. For most silicon and SiC MOSFETs V_GS(th) falls as the device heats up, so a gap that is fine at room temperature shrinks on a hot heatsink. The datasheet for the device usually gives V_GS(th) against temperature; take the low end of the range at maximum temperature, not the typical room-temperature value.

Measure in both current directions and at the largest current. In a hard-switched leg the outgoing device's turn-off depends on the current it is carrying, and whether the switch node moves during the dead time depends on the current's sign. The worst case for overlap and the worst case for diode conduction are different operating points.

The low-side gate is easy: a passive probe with a short spring ground clipped directly at the Kelvin source pin, not at a ground somewhere else on the board. The high-side gate is the hard part, because its reference is the switch node, which moves by the whole bus voltage in a few nanoseconds. A conventional differential probe sees that swing as common-mode voltage, and at tens of volts per nanosecond its finite common-mode rejection shows up as false spikes on the gate trace that are easy to mistake for Miller turn-on. An optically isolated probe, or at least a differential probe whose common-mode rejection is specified at the frequencies of your edges, is the tool for this measurement.

Deskew the two channels before trusting the result. Probes and cables can differ in delay by several nanoseconds, which is a significant fraction of a 50 to 200 ns dead time. Feed both probes from the same fast edge, align them, and only then read the interval between the two threshold crossings.

Probe at reduced bus voltage first. A probe ground clip accidentally placed on the switch node at full voltage can damage the oscilloscope, the probe or the board.

Even with a generous dead time, the off device can turn on by itself. When its partner switches on, the drain of the off device rises at the switch-node dv/dt, and the current C_gd · dv/dt flows through the gate-drain capacitance into the gate. That current has two places to go: into C_gs, raising the gate voltage, or out through the turn-off path to the driver. A simple first-order model with linear capacitances gives:

Gate voltage during the edge

v_gs(t) = V_off + C_gd · (dv/dt) · R · (1 − e^(−t/τ)), τ = R · (C_gs + C_gd)

Edge duration

t_edge = V_bus / (dv/dt)

Upper bound when the driver sinks nothing

Δv_gs ≈ C_gd · ΔV / (C_gs + C_gd) ≈ (C_gd / C_gs) · ΔV

Here R is everything in the turn-off path: external gate resistor, internal gate resistance and the driver's pull-down resistance. With illustrative values for a SiC leg, 800 V at 50 V/ns, an effective C_gd of 15 pF, C_gs of 1.5 nF and 6 Ω in the turn-off path, the edge lasts 16 ns, τ is about 9 ns, and the gate rises about 3.7 V above its off-state level. With a 0 V off-state and a hot threshold near 2 V, that is enough to partly turn the device on during the edge. With −4 V off-state bias the peak stays near −0.3 V. Cutting the turn-off path to 2 Ω brings the rise down to about 1.5 V. An active Miller clamp achieves a similar effect differently: it does not change R_g, it adds a separate low-impedance path from the gate to the off-rail.

This is an estimate, not a prediction. Real C_gd is strongly nonlinear and much larger at low drain voltage, so the early part of the edge injects more current than a single effective value suggests. Common-source inductance adds its own induced voltage during the current transition. Use the model to compare options, and confirm with a measurement.

1. 1Run a double-pulse test at reduced bus voltage with both gates and the switch node probed, deskewed as above. Confirm the probes show no spikes when only the switch node moves.
2. 2Raise to full bus voltage and the largest current, in both current directions. Read the gap between the two threshold crossings for each edge.
3. 3Add a current measurement in the DC-link loop, such as a coaxial shunt or a Rogowski coil around a device lead. A shoot-through shows up as an extra current spike at the moment of switching that is not explained by output capacitance charging.
4. 4Repeat with the heatsink at its maximum temperature. The gap usually shrinks and the Miller-induced rise matters more because the threshold is lower.
5. 5If you need to know how much margin is left, step the programmed dead time down in small increments at reduced voltage and watch the DC-link current. The point where the spike starts to grow is your real lower limit; the production value should sit well above it.

The measured gap is what you compare against the required minimum from the switch and driver data. The dead-time calculator on this site computes that minimum and the timer counts; the guide on dead-time voltage distortion shows what each extra nanosecond costs in an inverter, which is the other side of the trade-off.

• STMicroelectronics, AN6551 "Parasitic turn-on evaluation in silicon carbide MOSFETs," Rev 1, August 2026.
• STMicroelectronics, AN5355 "Mitigation technique of the SiC MOSFET gate voltage glitches with Miller clamp."
• Wolfspeed, PRD-06933 "Capacitance Ratio and Parasitic Turn-on," Rev. 1, January 2023.