Dead-Time Voltage Distortion in Three-Phase Inverters

During dead time both switches of a leg are off, and the output is decided by whichever diode carries the load current. If the current flows out of the leg, the lower diode conducts and the output sits at the negative rail, even though the controller wanted the upper switch to turn on. If the current flows into the leg, the upper diode conducts and the output sits at the positive rail. Either way the leg produces the voltage the current pushes it to, not the one that was commanded.

This happens once per switching period at the edge where the incoming switch is delayed. Averaged over the period, the leg voltage is short by a fixed amount whose sign is set by the current direction:

Average error of one leg

Δv = −sign(i) · t_dead · f_s · V_dc

Example (540 V, 8 kHz, 3 µs)

ΔV = 3 µs · 8 kHz · 540 V ≈ 13.0 V

So the error is a square wave in phase with the current, not with the voltage. It does not depend on load magnitude, only on the current's sign, which is why it hurts most when the commanded voltage is small.

A square wave of amplitude ΔV contains every odd harmonic with amplitude 4ΔV/(nπ). In a three-phase load with an isolated neutral, the triplen components (3rd, 9th, …) are common to all three legs and drop out of the phase-to-neutral voltage, which turns the per-leg square wave into the familiar six-step staircase. What remains is a fundamental component opposing the current and a 5th, 7th, 11th, 13th series.

Fundamental lost (opposes the current)

4ΔV / π

n-th harmonic, n = 5, 7, 11, 13, …

4ΔV / (nπ)

For the drive above, the fundamental shortfall is 4 · 13.0 / π ≈ 16.5 V and the 5th harmonic about 3.3 V. With sine PWM at m = 0.9 the commanded phase peak is 0.9 · 270 V = 243 V, so the loss is 6.8 % and the 5th harmonic 1.4 %. Drop to a tenth of rated speed with a plain V/f profile and the command falls to about 24 V. The error does not shrink, so the loss becomes roughly 68 % and the 5th harmonic about 14 % of what was asked for. In a motor the 5th and 7th harmonic currents combine into a torque ripple at six times the electrical frequency, which shows up as vibration and audible noise at low speed.

Change the numbers below to see the averaged phase voltage over one electrical cycle. Lower the modulation index to imitate low speed, or set a SiC case such as 800 V, 20 kHz and 200 ns: the leg error is then 3.2 V, about 1.1 % of the fundamental at m = 0.9.

The waveform is the switching-period average from the ideal model above. It ignores device switching delays, conduction drops and the current ripple near zero crossings, all discussed below.

The real error is not exactly t_dead · f_s · V_dc. The turn-on and turn-off delays of the switches stretch or shorten the effective dead time, so the useful quantity is the effective gap (t_dead + t_on − t_off), which depends on current, temperature and gate resistance. The forward drops of the switch and diode add a further current-dependent term. And near each zero crossing the ripple current changes sign several times within a few switching periods, so the error does not jump cleanly from +ΔV to −ΔV; it ramps through a region of a few amperes. In the current waveform this shows up as the flat step, often called zero-current clamping, that the square-wave model only approximates.

Since the error is predictable, the controller can add it back: for each phase, add +ΔV to the voltage command when the current is positive and −ΔV when it is negative, usually by lengthening or shortening that phase's compare value by t_dead (or the effective gap). The difficulty is knowing the sign of the current exactly where it matters, at the zero crossing. Measured current is noisy and contains ripple, so practical schemes either use the current reference instead of the measurement, use the current vector angle in the rotating frame, or soften the step into a ramp over a few amperes so that a wrong sign estimate costs less. Choi and Sul's 1996 paper is a widely cited example of a scheme that also accounts for the switching delays and device drops.

Compensation reduces the low-order harmonics but does not remove the root cause. The cleanest fix is still a shorter dead time, which is why it pays to size it from the switch and driver data rather than copying a value. The dead-time calculator on this site works through that sizing; the companion guide on choosing dead time covers the shoot-through side of the trade-off.

• J.-W. Choi and S.-K. Sul, "Inverter Output Voltage Synthesis Using Novel Dead Time Compensation," IEEE Transactions on Power Electronics, 1996.