How it works
The two legs of a phase-shifted full bridge switch under very different conditions. The leading leg turns off at the end of the power interval, while the output inductor is still reflected into the primary. That current is large and nearly constant, so it charges and discharges the switch-node capacitance linearly and quickly. The lagging leg turns off at the end of the freewheeling interval. Both rectifiers conduct then, the transformer is effectively shorted, and the only energy left to swing the node is what is stored in the leakage plus any series (shim) inductance L_r.
That makes the lagging leg a resonant transition between L_r and C_eq = 2·C_oss + C_tr. The node reaches the opposite rail only if ½·L_r·I_lag² ≥ ½·C_eq·V_in², which is the same as I_lag ≥ V_in/Z0 with Z0 = √(L_r/C_eq). If the current is smaller, the voltage turns around before it gets there and the switch turns on with the remaining voltage across it.
Having enough energy is not sufficient; the dead time has to fall inside a window. The drain reaches the rail at t1 = asin(V_in/(I_lag·Z0))/ω_r. From then the body diode carries the current, which ramps down at V_in/L_r and reaches zero at t2. If the gate turns on after t2 the current has reversed and the node swings back. The window shrinks with load, and at the energy limit both ends meet at the quarter resonant period. A dead time equal to that quarter period, (π/2)·√(L_r·C_eq), stays inside the window at every load where the energy suffices.
Lagging-leg current is evaluated at the valley of the output inductor current, (I_o − ΔI_Lo/2)/n, plus the magnetizing peak; leading-leg current at the inductor peak. The chart sweeps load from 4 % to 100 % and draws t1, t2, the lagging dead time and the leading-leg transition time, so you can read where each one stops working.
Design procedure
- 1Enter the operating point at the input voltage where ZVS is hardest to keep, usually the highest V_in.
- 2Read the energy limit I_o,min. If it is higher than the lightest load where you want ZVS, increase L_r or reduce C_eq (smaller or faster MOSFETs, less node capacitance).
- 3Set the lagging-leg dead time near the quarter resonant period shown in the results, then check the chart: the dashed dead-time line should stay between t1 and t2 over the load range you care about.
- 4Check the leading-leg transition time against its dead time at the lightest load of interest.
- 5Check the commanded duty D_cmd at minimum input voltage and full load. If it approaches 100 %, the transformer turns ratio or L_r has to change.
- 6Confirm on the bench with V_ds and the primary current; C_oss nonlinearity and stray capacitance move the real window.
Formulas
- Effective duty and output ripple
- D_eff = n·V_o / V_in, ΔI_Lo = V_o·(1 − D_eff)·T_s/2 / L_o (ripple at 2·f_s)
- Magnetizing peak
- I_m = V_in·D_eff·(T_s/2) / (2·L_m)
- Leg currents
- I_lead = (I_o + ΔI_Lo/2)/n + I_m, I_lag = (I_o − ΔI_Lo/2)/n + I_m
- Lagging-leg energy condition
- ½·L_r·I_lag² ≥ ½·C_eq·V_in², C_eq = 2·C_oss + C_tr ⇔ I_lag ≥ V_in / Z0, Z0 = √(L_r / C_eq)
- Lagging-leg ZVS window
- t1 = asin(V_in / (I_lag·Z0)) / ω_r, t2 = t1 + L_r·I_lag·cos(ω_r·t1) / V_in, ω_r = 1/√(L_r·C_eq); t_quarter = (π/2)·√(L_r·C_eq)
- Leading-leg transition
- t_lead = C_eq·V_in / I_lead
- Minimum load for lagging ZVS (energy)
- I_o,min = n·(V_in/Z0 − I_m) + ΔI_Lo/2
- Duty-cycle loss
- ΔD ≈ 4·L_r·I_lag·f_s / V_in (primary current reverses from +I to −I through L_r), D_cmd = D_eff + ΔD
Worked example
Defaults: a 400 V bus to 48 V at 1.5 kW (31.25 A), 5:1 transformer, 100 kHz, L_o = 20 µH, L_m = 1 mH, L_r = 15 µH and C_oss = 200 pF per switch. D_eff = 0.6, the output ripple is 4.8 A and the magnetizing peak 0.6 A, so the lagging leg sees 6.37 A at full load and needs only 2.07 A (C_eq = 400 pF, Z0 = 194 Ω). On energy alone ZVS holds down to 9.73 A, 31 % load. With the default 200 ns lagging dead time, though, ZVS stops at 76 % load: below that the diode current has already reached zero before the gate turns on (t2 falls below 200 ns). Setting the dead time to the quarter period, 122 ns, recovers ZVS down to about 32 %, just above the 31 % energy limit. The 15 µH costs 9.6 % of duty, so the controller must command about 70 %. Doubling L_r to 30 µH extends ZVS to 21 % load but doubles the duty loss to 19 %. These numbers were checked against an independent Python calculation, and t1 against a numerical integration of the L_r–C_eq transition.
Common mistakes
- Using the small-signal C_oss at high voltage. It understates the energy needed; use the energy-related value.
- Forgetting the transformer winding capacitance and probe or snubber capacitance at the switch node, all of which add to C_eq.
- Picking a long lagging dead time 'to be safe'. Past t2 the node swings back and ZVS is lost.
- Sizing L_r for ZVS at very light load without checking the duty loss at low line.
- Ignoring the magnetizing current. It helps both legs, and a deliberately lower L_m is one way to extend ZVS, at the cost of circulating current.
Frequently asked questions
Why does the leading leg almost always achieve ZVS?
At the leading-leg transition the output inductor is still reflected into the primary, so the switch node is driven by roughly I_o/n, a stiff current source. In the default example that charges 400 pF through 400 V in about 22 ns. Only at very light load, when the reflected current is small, does the leading leg need more than a typical dead time.
What value of C_oss should I enter?
For the energy condition use the energy-related output capacitance C_o(er) at the bus voltage from the MOSFET datasheet; for timing the time-related C_o(tr) is closer. Superjunction MOSFETs have a very nonlinear C_oss, so the two can differ by a factor of several, and the result shifts accordingly. Add the transformer winding capacitance and any snubber capacitor at the switch node to C_tr.
Why is a longer dead time not always safer?
After the node reaches the rail, the body diode conducts only until the current in L_r has ramped down to zero. If the gate turns on later than that, the current has reversed, the node has started to swing back, and the switch turns on with voltage across it. That is why the calculator reports both ends of the window and why the default 200 ns example loses ZVS below 76 % load even though there is enough energy down to 31 %.
Should I add a shim inductor or rely on the leakage?
A larger L_r lowers the load where lagging-leg ZVS is lost, but it also delays the current reversal, which shows up as duty-cycle loss and more circulating current during freewheeling. TI's SLUA560 example sizes the shim inductor for ZVS from full load down to 50 % load. Where to stop depends on how much light-load efficiency matters compared with full-load conduction loss and the duty headroom at minimum input voltage.
What is not modeled?
Conduction losses during freewheeling, the voltage drop of the rectifiers, secondary-side ringing, the nonlinearity of C_oss, adaptive dead-time control and the detailed behavior when the output inductor runs discontinuous. Below the DCM boundary the lagging current is taken as the magnetizing current only, which is a rough estimate.
Results are engineering estimates. Verify your design with datasheets, simulation and measurement.