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DAB Converter Design

Design a Dual Active Bridge (DAB) DC-DC converter and calculate its key parameters. Supports three modulation strategies: SPS, DPS and TPS.

Modulation Strategy

SPS (Single Phase Shift) Mode

Common Input Parameters

Design Strategy

Operating Point

ZVS conditions satisfied

ZVS conditions satisfied

Both necessary and sufficient ZVS conditions are met for the lagging full bridge.

Design Results

Voltage conversion ratio M

1.0000

Phase shift d

0.3500

Series inductance L_k (V1 side)

2.6208 µH

Average output current

2.5000 A

Output power

1000.00 W

Inductor peak current I1

32.0513 A

Inductor peak current I2

32.0513 A

How it works

A dual active bridge (DAB) converter connects two full bridges through a high-frequency transformer and a series inductance. Power flows from the leading bridge to the lagging bridge, and its amount is set by the phase shift between the two square-wave voltages. Because both bridges are active, power can flow in either direction, which makes DAB a common choice for battery chargers, energy storage and solid-state transformers.

V1H-bridge 1v_pL1 : nH-bridge 2v_sV2Pv_pv_si_Ld·T/2
Top: two full bridges linked by a series inductance L and a 1:n transformer. Bottom: with SPS, the secondary voltage v_s lags the primary voltage v_p by d·T/2; the inductor current i_L (shown for M = 1) ramps only while the two voltages differ.

Single phase shift (SPS) modulation uses one phase shift d between the bridges. It is simple but circulates large reactive currents when the voltage conversion ratio M is far from 1. Dual phase shift (DPS) adds an inner phase shift inside each bridge, and triple phase shift (TPS) uses independent inner shifts, both of which reduce current stress and widen the ZVS range.

For SPS, this calculator designs the series inductance from your maximum power and a chosen maximum phase shift, then solves for the phase shift at the selected operating point. It also checks the necessary and sufficient zero-voltage switching conditions, including the effect of the switches' parasitic capacitance.

DPS and TPS results are normalized to a base power P_N so that different designs can be compared directly. In these modes, enter L referred to the V2 side; to reuse an SPS result, multiply L_k by n². Here d is a fraction of half the switching period and n = N2/N1. Conventions differ between papers, so check these definitions before comparing with other references.

Design procedure

  1. 1Fix the operating range: V1, the minimum and maximum of V2, the power range and the switching frequency.
  2. 2Choose the turns ratio so that M = V2 / (n · V1) is close to 1 over the most common operating range; ZVS and RMS current are best near M = 1.
  3. 3Choose the maximum phase shift d_max for full power. A smaller d_max means a smaller inductance and lower RMS current but less control headroom; values around 0.25 to 0.35 are common.
  4. 4Compute the series inductance from the power equation at the maximum power point, then check the phase shift and ZVS conditions at the other corners of the range.
  5. 5If ZVS is lost or the RMS current is too high at light load or when M is far from 1, move to DPS or TPS modulation and compare the current stress.

Formulas

Voltage conversion ratio
M = V2 / (n · V1)
SPS transferred power (L_k referred to the V1 side)
P = d · (1 − d) · V1 · V2 / (2 · n · f_s · L_k)
Series inductance (design 1)
L_k = (1 − d_max) · d_max · V1 · V2_max / (2 · n · f_s · P_max)
Base power for DPS/TPS (L referred to the V2 side)
P_N = n · V1 · V2 / (8 · f_s · L)

Worked example

With V1 = 48 V, V2 = 400 V, 1 kW at 100 kHz and d_max = 0.35, leaving n empty sets n = V2_max / V1 ≈ 8.33 so M = 1 at full power. The design gives L_k ≈ 2.6 µH on the V1 side and an inductor peak current of about 32 A.

Common mistakes

  • Mixing conventions for n, d and the side to which L is referred. Check which side each formula assumes before comparing with a paper or a simulation.
  • Using d close to 0.5 at full power. Power is maximum at d = 0.5, so there is no control margin left for transients.
  • Ignoring the transformer leakage inductance, which adds to the external series inductance.
  • Checking ZVS only at full power. SPS usually loses ZVS first at light load when M ≠ 1.

Frequently asked questions

When should I use DPS or TPS instead of SPS?

When the voltage conversion ratio moves far from 1, for example with a wide battery voltage range, SPS loses ZVS at light load and its RMS current rises. DPS and TPS reduce both problems at the cost of more complex control.

What does the phase shift d mean?

d is the phase shift between the two bridge voltages as a fraction of half a switching period. Normal operation uses 0 < d ≤ 0.5; maximum power transfer happens at d = 0.5.

Why does the ZVS check include parasitic capacitance?

The inductor current at the switching instant must be large enough to charge and discharge the switch output capacitances before the next switch turns on. Larger capacitance needs more current.

Results are engineering estimates. Verify your design with datasheets, simulation and measurement.

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