How it works
A flyback stores energy in the transformer's magnetizing inductance while the switch is on and releases it to the secondary while the switch is off. The turns ratio fixes the reflected voltage V_or = n·(V_out + V_f) that the primary sees during the off time. A higher V_or shortens the off time, lowers the primary current and raises the drain stress; a lower V_or does the opposite. The ratio is set at minimum input, where the duty cycle is largest.
The magnetizing inductance follows from the conduction mode chosen at V_in,min and full load. In CCM it comes from the ripple ratio r = ΔI/I_c; in DCM it is a fraction of the critical inductance that puts the converter exactly on the boundary. The same inductance is then checked at V_in,max. A CCM design usually ends up close to, or inside, DCM at high line, and the boundary load in the table shows where the transition happens.
Leakage inductance is not coupled to the secondary, so its energy cannot reach the output. At turn-off it charges the RCD clamp, which holds the drain at V_in + V_clamp until the leakage current has decayed. The clamp loss grows with V_clamp/(V_clamp − V_or), so a clamp voltage close to V_or dissipates far more than the leakage energy alone. The leakage current decays in t_reset = L_lk·I_pk/(V_clamp − V_or).
The core is not designed here. What the core must handle is the inductance L_m at the peak current I_pk, or the energy ½·L_m·I_pk², without saturating. Core size, turns and gap come from the core maker's data, after which the measured leakage goes back into the clamp calculation.
Design procedure
- 1Set the input range. For an AC line, enter the lowest bulk-capacitor voltage at minimum line and full load, not just √2·V_ac,min.
- 2Choose D_max or V_or. Check that V_in,max + V_clamp stays inside the MOSFET rating with derating, and that the output diode's reverse voltage V_out + V_in,max/n is acceptable.
- 3Pick CCM with a ripple ratio, or DCM with L_m/L_crit, and read off L_m and the currents at V_in,min.
- 4Look at the V_in,max column: conduction mode, peak current and boundary load. The larger of the two peak currents defines the current limit and the core's saturation check.
- 5Estimate the leakage and size the clamp: R, C, the resistor's power rating and the leakage reset time.
- 6Choose the core and gap for ½·L_m·I_pk², then measure the real leakage and repeat the clamp calculation.
Formulas
- Turns ratio and maximum duty
- V_or = n·(V_out + V_f), D_max = V_or / (V_or + V_in,min − V_ds,on)
- CCM magnetizing current and inductance
- P_in = P_out/η, I_c = P_in / (V_in·D), ΔI = V_in·D / (f_s·L_m), L_m = V_in,min·D_max / (f_s·r·I_c)
- DCM and boundary
- L_crit = (V_in,min·D_max)² / (2·f_s·P_in), L_m = k·L_crit, I_pk = √(2·P_in / (L_m·f_s)), D₂ = I_pk·L_m·f_s / V_or
- RMS currents
- CCM: I_p,rms = √(D·(I_c² + ΔI²/12)), I_s,w = n·√((1 − D)·(I_c² + ΔI²/12)); DCM: I_p,rms = I_pk·√(D/3), I_s,w = n·I_pk·√(D₂/3); I_s,avg = I_out, I_s,rms = I_s,w · I_out / (P_in/(V_out + V_f))
- Voltage stress and stored energy
- V_ds,pk = V_in,max + V_clamp, V_R = V_out + V_in,max / n, E = ½·L_m·I_pk²
- RCD clamp
- P_clamp = ½·L_lk·I_pk²·f_s·V_clamp / (V_clamp − V_or), R = V_clamp² / P_clamp, C = 1 / ((ΔV_c/V_c)·R·f_s)
- Boundary load and RHP zero
- I_o,crit = η·V_in·D·ΔI / (2·V_out), f_RHP = (1 − D)²·R_L·n² / (2π·D·L_m), R_L = V_out / I_out
- Clamp reset time
- t_reset = L_lk · I_pk / (V_clamp − V_or)
Worked example
Defaults: 85–265 VAC with a 90 V bulk valley at 85 V, so V_in runs from 90 V to 375 V; 12 V at 2 A, η = 85 %, 65 kHz, V_f = 0.5 V, D_max = 0.45 and CCM with r = 0.8. The turns ratio comes out at 5.89 (V_or = 73.6 V) and L_m = 1.12 mH. At 90 V the primary peaks at 0.976 A with a 0.418 A valley and carries 0.480 A rms; the secondary peaks at 5.75 A and carries 2.77 A rms, of which 1.91 A rms is ripple in the output capacitor. At 375 V the duty drops to 16.4 % and the valley to 0.035 A, so the stage is just in CCM at full load and enters DCM below about 1.85 A. The drain sees 448 V without the spike and 485 V with V_clamp = 110 V, under the 520 V allowed at 80 % of a 650 V rating; the output diode sees 75.6 V. With 1 % leakage (11.2 µH) the clamp dissipates 1.04 W, 4.3 % of the output, using 11.8 kΩ and 13 nF for 10 % ripple. The RHP zero at 90 V is 19.9 kHz, so the crossover belongs below about 6.3 kHz. Switching to DCM with L_m = 0.8·L_crit gives 358 µH, a 1.56 A primary peak and a 9.18 A secondary peak.
Common mistakes
- Taking √2·V_ac,min as the minimum input. The bulk valley is lower, so the duty at low line exceeds the design value and the controller may reach its duty limit.
- Placing V_clamp only slightly above V_or. The clamp then takes energy that should go to the output, and its loss rises several-fold.
- Checking saturation only at the full-load peak. Start-up and overload run up to the current limit, which is higher, so the core has to hold the inductance there.
- Comparing V_in,max + V_clamp directly with the MOSFET rating. Clamp diode forward recovery and layout inductance add an overshoot above V_clamp, which is what the derating margin is for.
- Sizing the output capacitor only for the load current. In a flyback its ripple current is comparable to or larger than I_out, and that rating often decides the capacitor.
Frequently asked questions
Should I design in CCM or DCM?
DCM gives a smaller inductance, no reverse recovery in the output diode and no RHP zero, but higher peak and RMS currents. CCM lowers the peak and RMS currents, which matters as the current rises, at the cost of a larger inductance and an RHP zero that limits the loop bandwidth. Compare the two columns of the table for your own numbers before choosing.
Why does the clamp loss rise so quickly when V_clamp approaches V_or?
While the clamp conducts, the leakage current falls at a rate set by V_clamp − V_or, and during that time the secondary is also pushing energy into the clamp. The factor V_clamp/(V_clamp − V_or) captures this. At 1.5·V_or the loss is three times the leakage energy per cycle; at 1.2·V_or it is six times.
How were the formulas checked?
With the inputs of TI application note U-165 (SLUA086): 32–72 V in, 5 V at 10 A, V_f = 0.8 V, a 1 V MOSFET drop, 70 kHz, n = 5, a ripple equal to half the peak (r = 2/3), and η = 5/5.8 so that the input power matches the note's assumption. The calculator returns D = 48.3 %, a 5.16 A peak, 2.58 A ripple, 2.74 A rms, 83 µH (rounded to 80 µH in the note), a 3.33 A boundary load, a 19.4 V diode reverse voltage and a 25.8 A secondary peak, all matching the note.
Why doesn't the calculator pick a core?
Core selection depends on the material, the allowed flux density and temperature rise, the winding window and insulation requirements, none of which follow from the power stage alone. The calculator gives the inductance and peak current that the core has to support; the core maker's area-product and gap data take it from there.
What does the RHP zero mean for the feedback loop?
In CCM, a step increase in duty first shortens the off time and briefly reduces the current delivered to the output before the magnetizing current catches up. That shows up as a right-half-plane zero, which adds phase lag and gain at the same time. It moves lower as the load rises and the input falls, so the loop must cross over well below its value at V_in,min and full load.
Results are engineering estimates. Verify your design with datasheets, simulation and measurement.