Closing the Voltage Loop of an LLC Converter

In normal operation an LLC runs on the inductive side of its gain curve, where raising the switching frequency lowers the output voltage. The small-signal plant from frequency command to output voltage therefore has a negative DC gain. The controller must act on the inverted error (V_out − V_ref instead of V_ref − V_out), or equivalently use negative gains. Getting this sign wrong turns the loop into positive feedback, and the output runs to a limit as soon as the loop is closed.

The same fact explains why the converter must never cross the gain peak. To the left of the peak the slope changes sign, the effective plant gain becomes positive, and the controller now pushes the operating point further into the capacitive region. A hard minimum-frequency clamp, set with margin above the full-load gain peak at minimum input voltage, is mandatory.

Well below the switching frequency, a useful approximation treats the LLC as a gain block followed by the output filter. The gain is the slope of the DC gain curve at the operating point, converted to volts per hertz; the output capacitor and load add a pole, and the capacitor ESR adds a zero. A digital controller adds a delay for sampling, computation and PWM update.

Plant gain at the operating point

K_f = dV_out / df_s (negative above resonance)

Output filter

G(s) = K_f · (1 + s·ESR·C_o) / (1 + s·(R + ESR)·C_o)

Delay phase at crossover

φ_delay = −360° · f_c · T_d

This model ignores the resonant tank dynamics, which add a pair of poles near the beat frequency |f_s − f_r|. When the converter runs far from resonance those poles move close to the crossover range and the simple model becomes optimistic. That is one reason to keep the crossover modest.

The slope of the gain curve is shallow near resonance and steep near the gain peak, and it changes with load. Across the input-voltage and load range, the plant gain of a practical LLC can easily vary by a factor of ten or more. A compensator tuned at one operating point can be sluggish at another and nearly unstable at a third.

• Tune at the operating point with the highest plant gain, so the crossover frequency and phase margin there are acceptable, then check that the loop is still fast enough where the gain is lowest.
• If the spread is too large, schedule the controller gain against the measured switching frequency or input voltage. Many digital LLC controllers do exactly this.
• Check light load separately. If the controller enters burst mode, the linear model no longer applies and the burst hysteresis sets the output ripple.

1. 1Choose a crossover frequency f_c well below the switching frequency, typically a tenth to a twentieth of the minimum switching frequency, and keep it below the beat frequency |f_s − f_r| at the worst operating point.
2. 2Budget the digital delay. A 15 µs total delay costs 360° · 2 kHz · 15 µs ≈ 11° of phase at a 2 kHz crossover, but 54° at 10 kHz. Delay, not the plant, often sets the highest usable crossover.
3. 3Place the PI zero (Ki/Kp in rad/s) a factor of about three to five below the crossover, so the integrator removes steady-state error without eating much phase at f_c.
4. 4Aim for at least 45° of phase margin and 6 dB of gain margin at every corner of the operating range, then confirm with a load-step test.

A digital PWM timer can only produce periods that are whole numbers of clock ticks. In up-down (center-aligned) mode the switching frequency is f_s = f_clk / (2·N), so one count changes the frequency by roughly f_s / N.

Frequency step per timer count

Δf ≈ f_s / N = 2 · f_s² / f_clk

Resulting output voltage step

ΔV_out ≈ |K_f| · Δf

At 100 kHz with a 100 MHz up-down counter, N = 500 and each count moves the frequency by about 200 Hz. With a plant gain of −0.18 mV/Hz, that is a 36 mV jump in output voltage per count. If that is larger than your regulation band, the integrator hunts between two counts and you get a limit cycle that looks like noise. High-resolution PWM, dithering or a faster timer clock removes the problem.

• Clamp the frequency command between a minimum (above the gain peak) and a maximum (light-load limit or burst entry), and stop the integrator from winding up while clamped.
• Start at a high frequency and sweep down during soft start, so the output rises from low gain and the inrush into the output capacitor stays small.
• Filter the voltage feedback just enough to remove switching ripple. Every filter pole near crossover costs phase.
• Measure the real loop with an injection transformer or a firmware frequency sweep. The model is a starting point; the measurement is the answer.

The LLC plant and PI Bode tool on this site starts from a 390 V half-bridge LLC delivering 48 V / 500 W, operating near 104 kHz with a plant gain of roughly −0.18 mV/Hz. With 1 000 µF of output capacitance, a 2.5 V sense divider and 15 µs control delay, auto-tuning for a 2 kHz crossover and 60° phase margin gives about 13.6 dB of gain margin. Moving the operating point toward the gain peak in the tool shows how quickly the plant gain grows and the margins shrink.

Once the gains are fixed, the PID code generator turns them into a discrete-time controller with anti-windup and output limits for your microcontroller.