Choosing Dead Time: Shoot-Through, Diode Loss and Voltage Error
发布 2026-10-22
Dead time is the short gap during which both switches of a half bridge are commanded off. Too short and the two switches overlap, shorting the DC bus through the leg. Too long and current flows through a diode instead of a switch, adding loss and, in inverters, distorting the output voltage. The right value is a balance, and this guide shows how to find it rather than copying a number from an old design.
What happens during dead time
When one switch turns off, the load current does not stop. It commutates to the other device's body diode (or, in GaN, its reverse-conduction path) and stays there until the other switch turns on. In a hard-switched leg the dead time is simply a safety gap. In a soft-switched converter it is also the interval in which the switch-node capacitance is charged by the load or resonant current, so it must be long enough for that transition to finish.
Lower bound: avoid shoot-through
The switch that is turning off must be fully off before the other one starts to conduct. From datasheet timing values measured at the gate resistance you will actually use:
- Minimum dead time (switch level)
- t_dead,min = t_d(off) + t_f − t_d(on)
- Add driver mismatch
- t_dead ≥ t_dead,min + Δt_prop (high-side vs low-side channel)
- Margin
- t_dead = (t_dead,min + Δt_prop) · (1 + margin)
- Datasheet switching times are measured under specific conditions. Turn-off delay grows with larger gate resistance and usually with temperature, so evaluate at the hottest operating point.
- Isolated gate drivers can have propagation-delay mismatch of tens of nanoseconds between channels. Datasheets give a maximum value; use it.
- When the timer converts the result into counts, round up, never down.
Upper bound: what extra dead time costs
Every nanosecond beyond the minimum is time when current flows through a diode. Two effects grow with it.
- Diode conduction loss per leg (two dead times per period)
- P_dt ≈ V_f · I · 2 · t_dead · f_s
- Average voltage error of an inverter leg
- ΔV ≈ t_dead · f_s · V_dc (sign follows the current direction)
The loss term matters most for wide-bandgap devices. A silicon MOSFET body diode drops roughly 0.7 to 1 V, but a SiC MOSFET body diode is typically around 3 to 4 V, and GaN reverse conduction with a negative off-state gate voltage can be similar. With 20 A, a 3.5 V drop, 100 ns dead time and 100 kHz switching, the dead time alone costs 3.5 · 20 · 2 · 100 ns · 100 kHz = 1.4 W per leg. Body-diode reverse recovery in silicon adds further loss on top.
The voltage error matters most in motor drives and grid inverters. With a 600 V DC link, 10 kHz switching and 2 µs of IGBT dead time, ΔV ≈ 2 µs · 10 kHz · 600 V = 12 V. Because its sign flips with the current direction, it produces a distortion at every current zero crossing, visible as low-order harmonics and torque ripple. Dead-time compensation in the controller adds the expected error back to the voltage command.
Soft-switching converters: a different lower bound
In LLC, phase-shifted full-bridge and DAB converters, the dead time must be long enough for the available current to swing the switch node from one rail to the other. If it is too short, the incoming switch turns on before the voltage reaches zero and part of the ZVS benefit is lost. If it is too long, the node rings back and the diode conducts for longer than needed.
- Approximate transition time
- t_transition ≈ 2 · C_oss,eq · V_bus / I_switch
Since the switching current changes with load, adaptive dead time, which is shorter at heavy load and longer at light load, is common in digital controllers.
Worked example
- 1A MOSFET with t_d(off) = 60 ns, t_f = 20 ns and t_d(on) = 15 ns needs at least 60 + 20 − 15 = 65 ns at the switch level.
- 2The isolated driver datasheet gives a maximum channel-to-channel mismatch of 10 ns, so the requirement becomes 75 ns.
- 3A 20 % margin for temperature and part variation gives 90 ns.
- 4On a 170 MHz timer one count is about 5.9 ns, so 90 ns is 15.3 counts. Rounding up to 16 counts gives 94 ns.
The dead time calculator on this site performs the datasheet and gate-charge estimates and the timer conversion, and shows the rounding error.
Verify on the bench
- Measure both gate-source voltages and the switch-node voltage with probes that have matched delays; a few nanoseconds of probe skew can hide or invent an overlap.
- Check at the hottest operating point and at the highest current, where turn-off is slowest.
- Look at the DC-bus current or the switch current for a sharp spike at each transition, which indicates overlap.
- Then try reducing the dead time step by step while watching efficiency and the spike, and keep the final value with margin above the point where the spike appears.
本指南说明一般工程原理。请务必通过数据手册、仿真和测量验证您的设计。